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lcd module specification products name:apax t1 4 a 2 3 5.7 cm(1 4.1 inch) xga(1024x768) 262k color tft lcd module 3 .3 v l preliminary specification this technical specification is tentative and it will be changed without notice. ?ia1~a?|3--?q x_?o????? 76 ?? 39 ?1 4 ? tel:02 - 87912868 fax:02 - 87912869 version. 1.0
2 / 2 contents 1.0 handling precautions 2.0 general description 2.1 characteristics 2.2 functional block diagram 3.0 absolute maximum ratings 4.0 optical characteristics 5.0 signal interface 5.1 connectors 5.2 signal pin 5.3 signal description 5.4 signal electrical characteristics 5.5 signal for lamp connector 6.0 pixel format image 7.0 parameter guide line for cfl inverter 8.0 interface timings 8.1 timing characteristics 8.2 timing definition 9.0 power consumption 10.0 power on/off sequence 11.0 mechanical characteristics
3 / 3 revision history revision date page description 4/11/2000 all first release to customers 8/25/2000 5 typical power consumption 5.2w ! 5.0w lamp power 3.8w ! 3.6w 7 ccfl ignition voltage 1600v ! 1400v max. 8 add color chromaticity coordinates 15 add ccfl power 3.6w add ccfl ignition voltage 1400v max. 9/6/2000 7 15 ccfl current max. rating 7.0ma ! 6.5ma ccfl current typical 6.0ma ! 5.5ma
4 / 4 1.0 handling precautions since front polarizer is easily damaged, pay attention not to scratch it. be sure to turn off power supply when inserting or disconnecting from input connector. wipe off water drop immediately. long contact with water may cause discoloration or spots. when the panel surface is soiled, wipe it with absorbent cotton or other soft cloth. since the panel is made of glass, it may break or crack if dropped or bumped on hard surface. since cmos lsi is used in this module, take care of static electricity and insure human earth when handling. do not open nor modify the module assembly. do not press the reflector sheet at the back of the module to any directions. in case if a module has to be put back into the packing container slot after once it was taken out from the container, do not press the center of the ccfl reflector edge. instead, press at the far ends of the cfl reflector edge softly. otherwise the tft module may be damaged. at the insertion or removal of the signal interface connector, be sure not to rotate nor tilt the interface connector of the tft module. after installation of the tft module into an enclosure (notebook pc bezel, for example), do not twist nor bend the tft module even momentary. at designing the enclosure, it should be taken into consideration that no bending/twisting forces are applied to the tft module from outside. otherwise the tft module may be damaged. cold cathode fluorescent lamp in lcd contains a small amount of mercury. please follow local ordinances or regulations for disposal. small amount of materials having no flammability grade is used in the lcd module. the lcd module should be supplied by power complied with requirements of limited power source(2.11, iec60950 or ul1950), or be applied exemption. the lcd module is designed so that the cfl in it is supplied by limited current circuit(2.4, iec60950 or ul1950). do not connect the cfl in hazardous voltage circuit.
5 / 5 2.0 general description t h i s spec i f i c at i on app li es to the 14.1 i nch c o l or t f t /l c d m odu l e . this module is designed for a display unit of notebook style personal computer. the screen format is intended to support the xga (1024(h) x 768(v)) screen and 262k colors (rgb 6-bits data driver). all input signals are lvds interface compatible. this module does not contain an inverter card for backlight. 2.1 display characteristics the following items are characteristics summary on the table under 25 condition: items unit specifications screen diagonal [mm] 357(14.1") active area [mm] 285.7(h) x 214.3(v) pixels h x v 1024(x3) x 768 pixel pitch [mm] 0.279(per one triad) x 0.279 pixel arrangement r.g.b. vertical stripe display mode normally white typical white luminance (icfl=6.0ma) [cd/m 2 ] 150typ.(5 points average) contrast ratio 200 : 1 typ. optical rise time/fall time rise time fall time [msec] @25 o c 20 typ., 30 max. 30 typ., 50 max. nominal input voltage vdd [volt] +3.3 typ. typical power consumption (vdd line + vcfl line) [watt] 5.0(w/o inverter, all black pattern) 1.4(vdd) typ., 3.6(lamp) typ. weight [grams] 550 max. (w/o inverter) physical size [mm] 298.5(w) x 226.5(h) x 6.0(d) max. electrical interface r/g/b data, 3 sync, signals, clock (4 pairs lvds) support color native 262k colors ( rgb 6-bit data driver ) temperature range operating storage (shipping) [ o c] [ o c] 0 to +50 -20 to +60
6 / 6 2.2 functional block diagram the following diagram shows the functional block of the 14.1 inches color tft/lcd tft array/cell vdd lcd controller lcd drive card backlight unit 1024(r/g/b) x 3 gnd dc-dc converter ref circuit y-driver x-driver rxin0 rxin1 rxin2 rxclkin (4 pairs lvds) jae fi-seb20p-hf fi-c3-a1 mating jae fi-s20s or fi-se20m jst bhsr-02vs-1 mating type sm02b-bhss-1-tb lamp connector(2pin)
7 / 7 3.0 absolute maximum ratings absolute maximum ratings of the module is as following: item symbol min max unit conditions logic/lcd drive voltage vdd -0.3 +4.0 [volt] input voltage of signal vin -0.3 vdd+0.3 [volt] ccfl inrush current icfll - 20 [ma] note 2 ccfl current icfl - 6.5 [ma] rms ccfl ignition voltage vs - 1,400 vrms operating temperature top 0 +50 [ o c] note 1 operating humidity hop 8 95 [%rh] note 1 storage temperature tst -20 +60 [ o c] note 1 storage humidity hst 5 95 [%rh] note 1 vibration 1.5 10-200 g hz shock 50 18 g ms half sine wave note 1 : maximum wet-bulb should be 39 and no condensation. note 2 : duration=50 msec. max.
8 / 8 4.0 optical characteristics the optical characteristics are measured under stable conditions as follows under 25 condition: item conditions typ. note viewing angle [degree] [degree] horizontal (right) @k R 10 (left) ? 40(min) 40(min) k: contrast ratio [degree] [degree] vertical (upper) @k R 10 (lower) ? ? 10(min) 30(min) contrast ratio 200 ? response time [msec] rising 20 30(max.) [msec] falling 30 50(max.) color red x 0.577 0.04 chromaticity red y 0.338 0.03 coordinates (cie) green x 0.310 0.03 green y 0.563 0.03 blue x 0.158 0.03 blue y 0.157 0.04 white x 0.310 0.03 white y 0.346 0.03 white luminance (ccfl 6.0ma) [cd/m 2 ] 150 (5points average)
9 / 9 5.0 signal interface 5.1 connectors physical interface is described as for the connector on module. these connectors are capable of accommodating the following signals and will be following components. connector name / designation for signal connector manufacturer jae type / part number fi-seb20p-hf mating housing/part number fi-s20s or fi-se20m or fi-s20s with shell mating contact/part number fi-c3-a1 connector name / designation for lamp connector manufacturer jst type / part number bhsr-02vs-1 mating type / part number sm02b-bhss-1-tb 5.2 signal pin pin# signal name pin# signal name 1 vdd 2 vdd 3 gnd 4 gnd 5 rxin0- 6 rxin0+ 7 gnd 8 rxin1- 9 rxin1+ 10 gnd 11 rxin2- 12 rxin2+ 13 gnd 14 rxclkin- 15 rxclkin+ 16 gnd 17 reserved 18 reserved 19 gnd 20 gnd
10 / 10 5.3 signal description the module using a lvds receiver. lvds is a differential signal technology for lcd interface and high speed data transfer device. transmitter shall be sn75lvds84 (negative edge sampling) or compatible . signal name description rxin0-, rxin0+ lvds differential data input(red0-red5, green0) rxin1-, rxin1+ lvds differential data input(green1-green5, blue0-blue1) rxin2-, rxin2+ lvds differential data input(blue2-blue5, hsync, vsync, dsptmg) rxclkin-, rxclkin0+ lvds differential clock input vdd +3.3v power supply gnd ground note : input signals shall be low or hi-z state when vdd is off.
11 / 11 internal circuit of lvds inputs are as following. the module uses a 100ohm resistor between positive and negative data lines of each receiver input r r r r sn75lvds86 or compatible signal input pin no. 6 8 9 11 12 14 15 5 rxin0+ rxin0- rxin1+ rxin1- rxin2+ rxin2- rxclkin+ rxclkin-
12 / 12 signal name description +red5 +red4 +red3 +red2 +red1 +red0 red data 5 (msb) red data 4 red data 3 red data 2 red data 1 red data 0 (lsb) red-pixel data red-pixel data each red pixel's brightness data consists of these 6 bits pixel data. +green 5 +green 4 +green 3 +green 2 +green 1 +green 0 green data 5 (msb) green data 4 green data 3 green data 2 green data 1 green data 0 (lsb) green-pixel data green-pixel data each green pixel's brightness data consists of these 6 bits pixel data. +blue 5 +blue 4 +blue 3 +blue 2 +blue 1 +blue 0 blue data 5 (msb) blue data 4 blue data 3 blue data 2 blue data 1 blue data 0 (lsb) blue-pixel data blue-pixel data each blue pixel's brightness data consists of these 6 bits pixel data. -dtclk data clock the typical frequency is 65.0 mhz. the signal is used to strobe the pixel data and dsptmg signals. all pixel data shall be valid at the falling edge when the dsptmg signal is high. dsptmg display timing this signal is strobed at the falling edge of -dtclk. when the signal is high, the pixel data shall be valid to be displayed. vsync vertical sync the signal is synchronized to -dtclk . hsync horizontal sync the signal is synchronized to -dtclk . note: output signals from any system shall be low or hi-z state when vdd is off.
13 / 13 5.4 signal electrical characteristics input signals shall be low or hi-z state when vdd is off. it is recommended to refer the specifications of sn75lvds86dgg(texas instruments) in detail. signal electrical characteristics are as follows; parameter condition min max unit vth differential input high volta g e ( vcm=+1.2v ) 100 [mv] vtl differential input low voltage(vcm=+1.2v) -100 [mv] lvds macro ac characteristics are as follows: min. max. clock frequency (t) 50mhz 67mhz data setup time (tsu) 600ps data hold time (thd) 600ps 5.5 signal for lamp connector pin # signal name 1 lamp high voltage 2 lamp low voltage thd tsu input clock input data t
14 / 14 6.0 pixel format image following figure shows the relationship of the input signals and lcd pixel format. r g b r g b r g b r g b r g b r g b r g b r g b 0 1 1022 1023 1st line 768th line
15 / 15 7.0 parameter guide line for cfl inverter parameter min typ max units condition white luminance ( 5 p oints avera g e ) 130 150 ? [ cd/m 2 ] ( ta =2 5 ) ccfl current(icfl) 2.0 5.5 6.5 rms [ma] (ta=25 ) note 2 ccfl frequency(fcfl) 40 50 60 [khz] (ta=25 ) note 3 ccfl ignition voltage(vs) ? ? 1400 rms[volt] (ta= 0 ) note 4 ccfl voltage (reference) (vcfl) ? 660 ? rms [volt] (ta=25 ) note 5 ccfl power consumption (pcfl) ? 3.6 ? [watt] (ta=25 ) note 5 note 1: *1 all of characteristics listed are measured under the condition using the adt test inverter. *2 in case of using an inverter other than listed, it is recommended to check the inverter carefully. sometimes, interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen. *3 in designing an inverter, it is suggested to check safety circuit ver carefully. impedance of cfl, for instance, becomes more than 1 [m ohm] when cfl is damaged. *4 generally, cfl has some amount of delay time after applying kick-off voltage. it is recommended to keep on applying kick-off voltage for 1 [sec] until discharge. *5 cfl discharge frequency must be carefully chosen so as not to produce interfering noise stripes on the screen. *6 reducing cfl current increases cfl discharge voltage and generally increases cfl discharge frequency. so all the parameters of an inverter should be carefully designed so as not to produce too much leakage current from high-voltage output of the inverter. note 2: it should be emplyed the inverter which has ?duty dimming?, if icfl is less than 4ma. note 3: cfl discharge frequency shouldbe carefully determined to avoid interference between inverter and tft lcd. note 4: cfl inverter should be able to give out a power that has a generating capacity of over 1,400 voltage. lamp units need 1,400 voltage minimum for ignition. note 5: calculator value for reference (icflvcfl=pcfl)
16 / 16 8.0 interface timings basically, interface timings should match the vesa 1024x768 /60hz (vg901101) manufacturing guide line timing. 8.1 timing characteristics symbol description min typ max unit fdck dtclk frequency 65.00 [mhz] tck dtclk cycle time 15.38 [nsec] tx x total time 1206 1344 2047 [tck] tacx x active time 129 1024 [tck] tbkx x blank time 90 320 [tck] hsync h frequency 48.363 [khz] hsw h-sync width 2 136 [tck] hbp h back porch 1 160 [tck] hfp h front porch 0 24 [tck] ty y total time 771 806 1023 [tx] tacy y active time 768 [tx] vsync frame rate (55) 60 61 [hz] vw v-sync width 1 6 [tx] vfp v-sync front porch 1 3 [tx] vbp v-sync back porch 7 29 63 [tx] note: hsw(h-sync width) + hbp(h-sync back porch) should be less than 515 tck.
17 / 17 8.2 timing definition 1344 dot 136 dot 160 dot 24 dot 1024 dot h-sync dsptm 38h 3h 29h 6h 768h v-sync dsptmg
18 / 18 9.0 power consumption input power specifications are as follows; symble parameter min typ max units condition vdd logic/lcd drive voltage 3.0 3.3 3.6 [volt] load capacitance 20uf pdd vdd power 1.4 [watt] all black pattern pdd max vdd power max 1.65 [watt] max pattern note idd idd current 420 ma all black pattern idd max idd current max 500 ma max pattern note vddrp allowable logic/lcd drive ripple voltage 100 [mv] p-p vddns allowable logic/lcd drive ripple noise 100 [mv] p-p note: vdd=3.3v
19 / 19 10. power on/off sequence vdd power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi-z state or low level when vdd is off. 90% 10% 10% 10% 90% 10ms max. 0 min. 0 min. 0 v 0 v vdd signals 10% 10% 180ms min. 0 min. 0 v lam p on 10% 10% 150ms min.
20 / 20 11.0 mechanical characteristics
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